Low-cost error detection through high-level synthesis

System-on-chip design is becoming increasingly complex as technology scaling enables more and more functionality on a chip. This scaling and complexity has resulted in a variety of reliability and validation challenges including logic bugs, hot spots, wear-out, and soft errors. To make matters worse, as we reach the limits of Dennard scaling, efforts to improve system performance and energy efficiency have resulted in the integration of a wide variety of complex hardware accelerators in SoCs. Thus the challenge is to design complex, custom hardware that is efficient, but also correct and reliable. High-level synthesis shows promise to address the problem of complex hardware design by providing a bridge from the high-productivity software domain to the hardware design process. Much research has been done on high-level synthesis efficiency optimizations. This thesis shows that high-level synthesis also has the power to address validation and reliability challenges through two solutions. One solution for circuit reliability is modulo-3 shadow datapaths: performing lightweight shadow computations in modulo-3 space for each main computation. We leverage the binding and scheduling flexibility of high-level synthesis to detect control errors through diverse binding and minimize area cost through intelligent checkpoint scheduling and modulo-3 reducer sharing. We introduce logic and dataflow optimizations to further reduce cost. We evaluated our technique with 12 high-level synthesis benchmarks from the arithmetic-oriented PolyBench benchmark suite using FPGA emulated netlist-level error injection. We observe coverages of 99.1% for stuck-at faults, 99.5% for soft errors, and 99.6% for timing errors with a 25.7% area cost and negligible performance impact. Leveraging a mean error detection latency of 12.75 cycles (4150x faster than end result check) for soft errors, we also explore a rollback recovery method with an additional area cost of 28.0%, observing a 175x increase in reliability against soft errors. Another solution for rapid post-silicon validation of accelerator designs is Hybrid Quick Error Detection (H-QED): inserting signature generation logic in a hardware design to create a heavily compressed signature stream that captures the internal behavior of the design at a fine temporal and spatial granularity for comparison with a reference set of signatures generated by high-level simulation to detect bugs. Using H-QED, we demonstrate an improvement in error detection latency (time elapsed from when a bug is activated to when it manifests as an observable failure) of two orders of magnitude and a threefold improvement in bug coverage compared to traditional post-silicon validation techniques. H-QED also uncovered previously unknown bugs in the CHStone benchmark suite, which is widely used by the HLS community. H-QED incurs less than 10% area overhead for the accelerator it validates with negligible performance impact, and we also introduce techniques to minimize any possible intrusiveness introduced by H-QED

Moral Grandstanding in Public Discourse: Status-Seeking Motives as a Potential Explanatory Mechanism in Predicting Conflict

Public discourse is often caustic and conflict-filled. This trend seems to be particularly evident when the content of such discourse is around moral issues (broadly defined) and when the discourse occurs on social media. Several explanatory mechanisms for such conflict have been explored in recent psychological and social-science literatures. The present work sought to examine a potentially novel explanatory mechanism defined in philosophical literature: Moral Grandstanding. According to philosophical accounts, Moral Grandstanding is the use of moral talk to seek social status. For the present work, we conducted six studies, using two undergraduate samples (Study 1, N = 361; Study 2, N = 356); a sample matched to U.S. norms for age, gender, race, income, Census region (Study 3, N = 1,063); a YouGov sample matched to U.S. demographic norms (Study 4, N = 2,000); and a brief, one-month longitudinal study of Mechanical Turk workers in the U.S. (Study 5, Baseline N = 499, follow-up n = 296), and a large, one-week YouGov sample matched to U.S. demographic norms (Baseline N = 2,519, follow-up n = 1,776). Across studies, we found initial support for the validity of Moral Grandstanding as a construct. Specifically, moral grandstanding motivation was associated with status-seeking personality traits, as well as greater political and moral conflict in daily life

On the Baryon, Lepton-Flavour and Right-Handed Electron Asymmetries of the Universe

Non-perturbative electroweak effects, in thermal equilibrium in the early universe, have the potential to erase the baryon asymmetry of the universe, unless it is encoded in a B-L asymmetry, or in some "accidentally" conserved quantity. We first consider the possibility that the BAU may be regenerated from lepton flavour asymmetries even when initially $B-L = 0$. We show that provided some, but {\it not} all the lepton flavours are violated by ${\Delta}L{\neq}0$ interactions in equilibrium, the BAU may be regenerated without lepton mass effects. We next examine the possibility of encoding the baryon asymmetry in a primordial asymmetry for the right-handed electron, which due to its weak Yukawa interaction only comes into chemical equilibrium as the sphalerons are falling out of equilibrium. This would also raise the possibility of preserving an initial baryon asymmetry when $B-L = 0$.Comment: LATEX File with 12 pages, one figure (not included); published in Phys. Lett B297 (1992) p11

On the Erasure and Regeneration of the Primordial Baryon Asymmetry by Sphalerons

We show that a cosmological baryon asymmetry generated at the GUT scale, which would be destroyed at lower temperatures by sphalerons and possible new B- or L-violating effects, can naturally be preserved by an asymmetry in the number of right-handed electrons. This results in a significant softening of previously derived baryogenesis-based constraints on the strength of exotic B- or L-violating interactions.Comment: 10 pp. LaTex (2 figures, included) UMN-TH-1201/9

Back to the crossroads of Flatbush--the junction--student housing for Brooklyn College

Thesis (M. Arch)--Massachusetts Institute of Technology, Dept. of Architecture, 1988.Bibliography: p. 65-67.The crossroads of Flatbush (often called The Junction) is a five point intersection of vehicular and pedestrian traffic. A crossroad where ethnic groups step beyond subtle neighborhood boundaries and merge to use public services and shops. Steel gates roll up at the beginning of each day and pushcarts slip onto the sidewalk. Pedestrians jostle vendors and vendors strike bargains. Senior citizens seeks unlit corners after tracing the sun's path. Night shift workers yawn while gradually adjusting to the morning rush. High school and college students dart in and out of donut shops as they make their way to classes. The electricity emitted from such an urban environment has a lasting effect. It is this energy that I wish to capture in my design exploration for student housing. The development of a physical form that would reflect the vibrancy of The Junction.by Keith A. Campbell.M.Arc

Robust and reliable hardware accelerator design through high-level synthesis

System-on-chip design is becoming increasingly complex as technology scaling enables more and more functionality on a chip. This scaling-driven complexity has resulted in a variety of reliability and validation challenges including logic bugs, hot spots, wear-out, and soft errors. To make matters worse, as we reach the limits of Dennard scaling, efforts to improve system performance and energy efficiency have resulted in the integration of a wide variety of complex hardware accelerators in SoCs. Thus the challenge is to design complex, custom hardware that is efficient, but also correct and reliable. High-level synthesis shows promise to address the problem of complex hardware design by providing a bridge from the high-productivity software domain to the hardware design process. Much research has been done on high-level synthesis efficiency optimizations. This dissertation shows that high-level synthesis also has the power to address validation and reliability challenges through three automated solutions targeting three key stages in the hardware design and use cycle: pre-silicon debugging, post-silicon validation, and post-deployment error detection. Our solution for rapid pre-silicon debugging of accelerator designs is hybrid tracing: comparing a datapath-level trace of hardware execution with a reference software implementation at a fine temporal and spatial granularity to detect logic bugs. An integrated backtrace process delivers source-code meaning to the hardware designer, pinpointing the location of bug activation and providing a strong hint for potential bug fixes. Experimental results show that we are able to detect and aid in localization of logic bugs from both C/C++ specifications as well as the high-level synthesis engine itself. A variation of this solution tailored for rapid post-silicon validation of accelerator designs is hybrid hashing: inserting signature generation logic in a hardware design to create a heavily compressed signature stream that captures the internal behavior of the design at a fine temporal and spatial granularity for comparison with a reference set of signatures generated by high-level simulation to detect bugs. Using hybrid hashing, we demonstrate an improvement in error detection latency (time elapsed from when a bug is activated to when it manifests as an observable failure) of two orders of magnitude and a threefold improvement in bug coverage compared to traditional post-silicon validation techniques. Hybrid hashing also uncovered previously unknown bugs in the CHStone benchmark suite, which is widely used by the HLS community. Hybrid hashing incurs less than 10% area overhead for the accelerator it validates with negligible performance impact, and we also introduce techniques to minimize any possible intrusiveness introduced by hybrid hashing. Finally, our solution for post-deployment error detection is modulo-3 shadow datapaths: performing lightweight shadow computations in modulo-3 space for each main computation. We leverage the binding and scheduling flexibility of high-level synthesis to detect control errors through diverse binding and minimize area cost through intelligent checkpoint scheduling and modulo-3 reducer sharing. We introduce logic and dataflow optimizations to further reduce cost. We evaluated our technique with 12 high-level synthesis benchmarks from the arithmetic-oriented PolyBench benchmark suite using FPGA emulated netlist-level error injection. We observe coverages of 99.1% for stuck-at faults, 99.5% for soft errors, and 99.6% for timing errors with a 25.7% area cost and negligible performance impact. Leveraging a mean error detection latency of 12.75 cycles (4150× faster than end result check) for soft errors, we also explore a rollback recovery method with an additional area cost of 28.0%, observing a 175× increase in reliability against soft errors. While the area cost of our modulo shadow datapaths is much better than traditional modular redundancy approaches, we want to maximize the applicability of our approach. To this end, we take a dive into gate-level architectural design for modulo arithmetic functional units. We introduce new low-cost gate-level architectures for all four key functional units in a shadow datapath: (1) a modulo reduction algorithm that generates architectures consisting entirely of full-adder standard cells; (2) minimum-area modulo adder and subtractor architectures; (3) an array-based modulo multiplier design; and (4) a modulo equality comparator that handles the residue encoding produced by the above. We compare our new functional units to the previous state-of-the-art approach, observing a 12.5% reduction in area and a 47.1% reduction in delay for a 32-bit mod-3 reducer; that our reducer costs, which tend to dominate shadow datapath costs, do not increase with larger modulo bases; and that for modulo-15 and above, all of our modulo functional units have better area and delay then their previous counterparts. We also demonstrate the practicality of our approach by designing a custom shadow datapath for error detection of a multiply accumulate functional unit, which has an area overhead of only 12% for a 32-bit main datapath and 2-bit modulo-3 shadow datapath. Taking our reliability solution further, we look at the bigger picture of modulo shadow datapaths combined with other solutions at different abstraction layers, looking to answer the following question: Given all of the existing reliability improvement techniques for application-specific hardware accelerators, what techniques or combinations of techniques are the most cost-effective? To answer this question, we consider a soft error fault model and empirically evaluate cross-layer combinations of ABFT, EDDI, and modulo shadow datapaths in the context of high-level synthesis; parity in logic synthesis; and flip-flop hardening techniques at the physical design level. We measure the reliability benefit and area, energy, and performance cost of each technique individually and for interesting technique combinations through FPGA emulated fault-injection and physical place-and-route. Our results show that a combination of parity and flip-flop hardening is the most cost-effective in general with an average 1.3% area cost and 5.7% energy cost for a 50× improvement in reliability. The addition of modulo-3 shadow datapaths to this combination provides some additional benefit for some applications, even without considering its combinational logic, stuck-at fault, and timing error protection benefits. We also observe new efficiency challenges for ABFT and EDDI when used for hardware accelerators

Cosmological 3-Brane Solutions

We analyze cosmological equations in the brane world scenario with one extra space-like dimension. We demonstrate that the cosmological equations can be reduced to the usual 4D Friedmann type if the bulk energy-momentum tensor is different from zero. We then generalize these equations to the case of a brane of finite thickness. We also demonstrate that when the bulk energy-momentum tensor is different from zero, the extra space-like dimension can be compactified with a single brane and show that the stability of the radius of compactification implies standard cosmology and vice versa. For a brane of finite thickness, we provide a solution such that the 4D Planck scale is related to the fundamental scale by the thickness of the brane. In this case, compactification of the extra dimension is unnecessary.Comment: 14 pages, Latex file, no figures, typos corrected, comments and references added, version to appear in Physics Letters

Does self-love lead to love for others?: A story of narcissistic game playing.

Five studies investigated the links among narcissism, self-esteem, and love. Across all studies, narcissism was associated primarily with a game-playing love style. This link was found in reports of general love styles (Study 1a) and of love in ongoing romantic relationships (Studies 1b–3, 5). Narcissists ’ game-playing love style was the result of a need for power and autonomy (Study 2) and was linked with greater relationship alternatives and lesser commitment (Study 3). Finally, narcissists ’ self-reports of game playing were confirmed by their partners in past and current relationships (Studies 4, 5). In contrast, self-esteem was negatively linked to manic love and positively linked to passionate love across studies. Implications for the understanding of narcissism in relationships are discussed. If you do not love yourself, you will be unable to love others. (Popular belief quoted by Branden, 1994) There are a whole lot of hearts breakin ’ tonight from the disease of conceit.—Bob Dylan, “Disease of Conceit” It is popularly believed that self-love is a necessary prerequisite for loving others. As exemplified by the first quote above, this belief permeates the realm of self-help literature (Branden, 1994)

Neutrino Mass Effects in a Minimally Extended Supersymmetric Standard Model

We consider an extension of the supersymmetric standard model which includes singlet Higgs superfield representations (in three generations) to generate neutrino masses via the see-saw mechanism. The resulting theory may then exhibit R-parity violation in the couplings of the singlets, inducing $R$-parity violating effective interactions among the standard model superfields, as well as inducing decay of the lightest neutralino, which otherwise would compose a stable LSP. We compute the rates for the resulting neutralino decays, depending on the particular superpotential couplings responsible for the violation of R-parity. We compare to astrophysical constraints on the decay of massive particles.Comment: 12 pages, plain LATEX, 3 non-LATEX figures available in hardcopy on request; one reference corrected; Alberta-THY-2/94, UMN-TH-1237/9